1. Technical Field of the Invention
The present invention relates generally to semiconductor memories. More particularly, and not by way of any limitation, the present invention is directed to a compact virtual ground diffusion programmable architecture as well as associated system, method and circuitry for read-only memory (ROM).
2. Description of Related Art
Silicon manufacturing advances today allow true single-chip systems to be fabricated on a single die (i.e., System-On-Chip or SOC integration). However, there exists a “design gap” between today's electronic design automation (EDA) tools and the advances in silicon processes which recognizes that the available silicon real-estate has grown much faster than has designers' productivity, leading to underutilized silicon. Unfortunately, the trends are not encouraging: the “deep submicron” problems of non-convergent timing, complicated timing and extraction requirements, and other complex electrical effects are making silicon implementation harder. This is especially acute when one considers that various types of circuitry such as analog blocks, non-volatile memory (e.g., read-only memory or ROM), random access memories (RAMs), and other “non-logic” cells are being required. The gap in available silicon capacity versus design productivity means that without some fundamental change in methodology, it will take several staff years to develop leading-edge integrated circuits (ICs).
Design re-use has emerged as the key methodology solution for successfully addressing this time-to-market problem in semiconductor IC design. In this paradigm, instead of re-designing every part of every IC chip, engineers can re-use existing designs as much as possible and thus minimize the amount of new circuitry that must be created from scratch. It is commonly accepted in the semiconductor industry that one of the most prevalent and promising methods of design re-use is through what are known as Intellectual Property (“IP”) components—pre-implemented, re-usable modules of circuitry that can be quickly inserted and verified to create a single-chip system. Such re-usable IP components are typically provided as megacells, cores, macros, embedded memories through generators or memory compilers, et cetera.
It is well known that memory, including ROM, is a key technology driver for SOC design. It is also well known that leakage and power consumption are two major factors in designing a high performance ROM core, especially where the device geometries continue to shrink. A traditional ROM cell comprises a single transistor, where the gate is connected to the word line, the drain is connected to the bit line and the source is connected to the ground. In a diffusion programmable ROM, the cell is programmed to store a logic 0 or 1 using the diffusion layer. One logic level is created by the presence of a transistor. On the other hand, the transistor is omitted to create the other logic level.
Diffusion programmable ROMs have been found to be useful because of their relative cell size advantage. However, in the traditional ROM architectures where the source terminals of the ROM cells are connected to ground, power consumption can be unacceptably high due to subthreshold leakage (i.e., static leakage) as well as functional leakage during access operations, especially in high density designs. In order to address this issue, separate source lines that are maintained at a precharged level have been implemented on a per-column basis in certain ROM designs. With respect to accessing such a ROM circuit for read operations, a particular source line is pulled low in order to create a virtual ground. Thereafter, the ROM cell can be read as a traditional ROM cell. Although this design is advantageous in reducing the leakage, the addition of source lines makes the cell size larger than the traditional ROM cell.